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em48am1684vtg jun. 2010 1/20 www.eorex.com revision history revision 0.1 (jun. 2010) - first release. -
em48am1684vtg jun. 2010 2/20 www.eorex.com 256mb (4m 4bank 16) synchronous dram features ? fully synchronous to positive clock edge ? single 3.3v 0.3v power supply ? lvttl compatible with multiplexed address ? programmable burst length (b/l) - 1, 2, 4, 8 or full page ? programmable cas latency (c/l) - 2 or 3 ? data mask (dqm) for read / write masking ? programmable wrap sequence ? sequential (b/l = 1/2/4/8/full page) ? interleave (b/l = 1/2/4/8) ? burst read with single-bit write operation ? all inputs are sampled at the rising edge of the system clock ? auto refresh and self refresh ? 8,192 refresh cycles / 64ms (7.8us) ordering information description the em48am1684vtg is synchronous dynamic random access memory (sdram) organized as 4meg words x 4 banks by 16 bits. all inputs and outputs are synchronized with the positive edge of the clock. the 256mb sdram uses synchronized pipelined architecture to achieve high speed data transfer rates and is designed to operate at 3.3v low power memory system. it also provides auto refresh with power saving / down mode. all inputs and outputs voltage levels are compatible with lvttl. available packages: tsopii 54p 400mil. part no organization max. freq package grade pb em48am1684vtg-6f 16m x 16 166mhz @cl3 54pin tsop(ll) commercial free EM48AM1684VTG-7F 16m x 16 143mhz @cl3 54pin tsop(ll) commercial free em48am1684vtg-75f 16m x 16 133mhz @cl3 54pin tsop(ii) commerical free em48am1684vtg-6fe 16m x 16 166mhz @cl3 54pin tsop(ll) extended free EM48AM1684VTG-7Fe 16m x 16 143mhz @cl3 54pin tsop(ll) extended free em48am1684vtg-75fe 16m x 16 133mhz @cl3 54pin tsop(ii) extended free
em48am1684vtg jun. 2010 3/20 www.eorex.com parts naming rules * eorex reserves the right to change products or specification without notice.
em48am1684vtg jun. 2010 4/20 www.eorex.com pin assignment 54pin tsop-ii
em48am1684vtg jun. 2010 5/20 www.eorex.com pin description (simplified) pin name function 38 clk (system clock) master clock input (active on the positive rising edge) 19 /cs (chip select) selects chip when active 37 cke (clock enable) activates the clk when ?h? and deactivates when ?l?. cke should be enabled at least one cycle prior to new command. disable input buffers for power down in standby. 23~26, 22, 29~36 a0~a12 (address) row address (a0 to a12) is determined by a0 to a12 level at the bank active command cycle clk rising edge. ca (ca0 to ca8) is determined by a0 to a8 level at the read or write command cycle clk rising edge. and this column address becomes burst access start address. a10 defines the pre-charge mode. when a10= high at the pre-charge command cycle, all banks are pre-charged. but when a10= low at the pre-charge command cycle, only the bank that is selected by ba0/ba1 is pre-charged. 20, 21 ba0, ba1 (bank address) selects which bank is to be active. 18 /ras (row address strobe) latches row addresses on the positive rising edge of the clk with /ras ?l?. enables ro w access & pre-charge. 17 /cas (column address strobe) latches column addresses on the positive rising edge of the clk with /cas low. enables column access. 16 /we (write enable) latches column addresses on the positive rising edge of the clk with /cas low. enables column access. 39/15 udqm/ldqm (data input/output mask) dqm controls i/o buffers. 2, 4, 5, 7, 8, 10, 11, 13, 42, 44, 45, 47, 48, 50, 51, 53 dq0~dq15 (data input/output) dq pins have the same function as i/o pins on a conventional dram. 1,14,27/ 28,41,54 v dd /v ss (power supply/ground) v dd and v ss are power supply pins for internal circuits. 3, 9, 43, 49/ 6, 12, 46, 52 v ddq /v ssq (power supply/ground) v ddq and v ssq are power supply pins for the output buffers. 40 nc (no connection) this pin is recommended to be left no connection on the device.
em48am1684vtg jun. 2010 6/20 www.eorex.com absolute maximum rating symbol item rating units v in , v out input, output voltage -0.3 ~ vcc 0.3 v v dd , v ddq power supply voltage -0.3 ~ +4.6 v commercial 0 ~ +70 t op operating temperature range extended -25 ~ +85 c t stg storage temperature range -55 ~ +150 c p d power dissipation 1 w i os short circuit current 50 ma note: caution exposing the device to stress above thos e listed in absolute maximum ratings could cause permanent damage. the device is not m eant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. capacitance (v cc =3.3v, f=1mhz, t a =25c) symbol parameter min. typ. max. units c clk clock capacitance - - 4 pf c i input capacitance for clk, cke, address, /cs, /ras, /cas, /we, dqml, dqmu - - 6.5 pf c o input/output capacitance - - 6.5 pf recommended dc operating conditions (t a =-25c ~85c) symbol parameter min. typ. max. units v dd power supply voltage 3.0 3.3 3.6 v v ddq power supply voltage (for i/o buffer) 3.0 3.3 3.6 v v ih input logic high voltage 2.0 - v cc +0.3 v v il input logic low voltage -0.3 - 0.8 v note : * all voltages referred to v ss . * vih may overshoot to vcc + 2.0 v for pulse width of < 4ns with 3.3v. vil may undershoot to -2.0v for pulse width < 4.0 ns with 3.3v. pulse widt h measured at 50% points with amplitude measured peak to dc reference.
em48am1684vtg jun. 2010 7/20 www.eorex.com recommended dc operating conditions (v dd =3.3v 0.3v, t a =0c ~70c) max. symbol parameter test conditions -6 -7 units i cc1 operating current (note 1) burst length=1, one bank t rc t rc (min.), i ol =0ma, one bank active 110 110 ma i cc2p cke v il (max.), t ck =min. 12 12 ma i cc2ps precharge standby current in power down mode cke v il (max.), t ck = v il (min.), /cs=v ih t ck = v il (max.), power down mode 35 35 ma i cc3n no operating current t ck =min. /cs=v ih(min.) 4banks active cke v il (min.) 65 65 ma i cc4 operating current (burst mode) (note 2) t ccd 2clks, i ol =0ma 105 100 ma i cc5 auto refresh current (note 3) t ck =min. 150 140 ma standard 6 6 ma i cc6 self refresh current, cke 0.2v low power 1.2 1.2 ma *all voltages referenced to v ss . note 1: i cc1 depends on output loading and cycle rates. specified values are obtained with the output open. input signals are changed only one time during t ck (min.) note 2: i cc4 depends on output loading and cycle rates. specified values are obtained with the output open. input signals are changed only one time during t ck (min.) note 3: input signals are changed only one time during t ck (min.) recommended dc operating conditions (continued) symbol parameter test conditions min. typ. max. units i il input leakage current 0 v i v ddq , v ddq =v dd all other pins not under test=0v -10 - +10 ua i ol output leakage current 0 v o v ddq , d out is disabled -10 - +10 ua v oh high level output voltage i o =-4ma 2.4 - - v v ol low level output voltage i o =+4ma - - 0.4 v
em48am1684vtg jun. 2010 8/20 www.eorex.com block diagram
em48am1684vtg jun. 2010 9/20 www.eorex.com ac operating test conditions (v dd =3.3v 0.3v, t a =0c ~70c) item conditions output reference level 1.4v/1.4v output load see diagram as below input signal level 2.4v/0.4v transition time of input signals 2ns input reference level 1.4v ac operating test characteristics (v dd =3.3v 0.3v, t a =0c ~70c) -6 -7 symbol parameter min. max.. min. max. units cl=3 6 - 7 - t ck clock cycle time cl=2 7.5 - 10 - ns cl=3 - 5.4 - 5.4 t ac access time form clk cl=2 - 5.4 - 6 ns t ch clk high level width 2 - 2.5 - ns t cl clk low level width 2 - 2.5 - ns cl=3 2.5 - 2.5 - t oh data-out hold time cl=2 - - - - ns cl=3 3 7 3 7 t hz data-out high impedance time (note 5) cl=2 - - - - ns t lz data-out low impedance time 1 - 1 - ns t hz data-out high impedance time 3 6 3 7 ns t ih input hold time 1 - 1 - ns t is input setup time 1.5 - 1.5 - ns t dqz dqm data out disable latency 2 2 clk t rsc mode register set-up time 12 - 14 - ns t sb power down mode entry time 0 6 0 7 ns t ds data-in set-up time 1.5 - 1.5 - ns t dh data-in hold time 1 - 1 - * all voltages referenced to v ss . note 5: t hz defines the time at which th e output achieve the open circuit condition and is not referenced to output voltage levels.
em48am1684vtg jun. 2010 10/20 www.eorex.com ac operating test characteristics (continued) (v dd =3.3v 0.3v, t a =0c ~70c/t a =-25c ~ +85c for extended grade) -6 -7 symbol parameter min. max.. min. max. units t rc active to active command period (note 6) 60 65 ns t ras active to precharge command period (note 6) 42 100k 45 100k ns t rp precharge to active command period (note 6) 18 20 ns t rcd active to read/write delay time (note 6) 18 20 ns t rrd active(one) to active(another) command (note 6) 12 15 ns t ccd read/write command to read/write command 1 1 clk t dpl date-in to precharge command 2 2 clk t bdl date-in to burst stop command 1 1 clk cl=3 3 3 t roh data-out to high impedance from precharge command cl=2 2 2 clk t srex self refresh exit time 1 1 clk t wr write recovery time, auto precharge 2 2 clk t dqw dqm write mask latency 0 0 clk t ref refresh time (8,192 cycle) 64 64 ms * all voltages referenced to v ss . note 6: these parameters account for the number of clock cycles and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing/clock period (count fractions as a whole number)
em48am1684vtg jun. 2010 11/20 www.eorex.com recommended power on and initialization the following power on and initialization sequence guarantees the device is pr econditioned to each users specific needs. (like a conventional dram) during power on, all vdd and vddq pins must be built up simultaneously to the specified voltage when the input signals are held in the ?nop? state. the power on voltage must not exceed vdd + 0.3v on any of the input pins or vdd supp lies. (clk signal started at same time) after power on, an initial pause of 200 s is requi red followed by a precharge of all banks using the precharge command. to prevent data contention on the dq bus during power on, it is required that the dqm and cke pins be held high during the initial pause period. once all banks have been precharged, the mode register set command must be issued to initialize the mode register. a mini mum of eight auto refresh cycles (cbr) are also required, and these may be done before or after programming the mode register.
em48amm1684vtg jun. 2010 12/20 www.eorex.com simplified state diagram
em48amm1684vtg jun. 2010 13/20 www.eorex.com address input for mode register set burst length sequential interleave a2 a1 a0 1 1 0 0 0 2 2 0 0 1 4 4 0 1 0 8 8 0 1 1 reserved reserved 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 full page reserved 1 1 1 cas latency a6 a5 a4 reserved 0 0 0 reserved 0 0 1 2 0 1 0 3 0 1 1 reserved 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 burst type a3 interleave 1 sequential 0 ba1 ba0 a12/a11 a10 a9 a8 a7 operation mode 0 0 0 0 0 0 0 burst read/burst write 0 0 0 0 1 0 0 burst read/single write ba1 ba0 a11/12 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 operation mode cas latency bt burst length
em48amm1684vtg jun. 2010 14/20 www.eorex.com burst type ( a3 ) burst length a2 a1 a0 sequential addressing interleave addressing x x 0 0 1 0 1 2 x x 0 1 0 1 0 x 0 0 0 1 2 3 0 1 2 3 x 0 11 2 3 0 1 0 3 2 x 1 0 2 3 0 12 3 0 1 4 x 1 1 3 0 1 2 3 2 1 0 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 11 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 12 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 8 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 full page * n n n cn cn+1 cn+2 ?... - * page length is a function of i/o organization and colu mn addressing x16 (ca0 ~ ca8): full page = 512bits 1. command truth table cke command symbol n-1 n /cs /ras /cas /we ba0, ba1 a10 a11, a9~a0 ignore command desl h x h x x x x x x no operation nop h x l h h h x x x burst stop bsth h x l h h l x x x read read h x l h l h v l v read with auto pre-charge reada h x l h l h v h v write writ h x l h l l v l v write with auto pre-charge writa h x l h l l v h v bank activate act h x l l h h v v v pre-charge select bank pre h x l l h l v l x pre-charge all banks pall h x l l h l x h x mode register set mrs h x l l l l l l v * h = high level, l = low level, x = high or low level (don?t care), v = valid data input
em48amm1684vtg jun. 2010 15/20 www.eorex.com 2. dqm truth table cke command symbol n-1 n /cs data write / output enable enb h x h data mask / output disable mask h x l upper byte write enable / output enable bsth h x l read read h x l read with auto pre-charge reada h x l write writ h x l write with auto pre-charge writa h x l bank activate act h x l pre-charge select bank pre h x l pre-charge all banks pall h x l mode register set mrs h x l * h = high level, l = low level, x = high or low level (don?t care), v = valid data input 3. cke truth table cke command command symbol n-1 n /cs /ras /cas /we addr. activating clock suspend mode entry h l x x x x x any clock suspend mode l l x x x x x clock suspend clock suspend mode exit l h x x x x x idle cbr refresh command ref h h l l l h x idle self refresh entry self h l l l l h x l h l h h h x self refresh self refresh exit l h h x x x x idle power down entry h l x x x x x power down power down exit l h x x x x x * h = high level, l = low level, x = high or low level (don't care), v = valid data input
em48amm1684vtg jun. 2010 16/20 www.eorex.com 4. operative command table (note 7) current state /cs /r /c /w addr. command action notes h x x x x desl nop or power down 8 l h h x x nop or bst nop or power down 8 l h l h ba/ca/a10 read/reada illegal 9 l h l l ba/ca/a10 writ/writa illegal 9 l l h h ba/ra act row activating l l h l ba, a10 pre/pall nop l l l h x ref/self refresh or self refresh 10 idle l l l l op-code mrs mode register accessing h x x x x desl nop l h h x x nop or bst nop l h l h ba/ca/a10 read/reada begin read : determine ap 11 l h l l ba/ca/a10 writ/writa begin write : determine ap 11 l l h h ba/ra act illegal 9 l l h l ba, a10 pre/pall pre-charge 12 l l l h x ref/self illegal 10 row active l l l l op-code mrs illegal h x x x x desl continue burst to end row active l h h h x nop continue burst to end row active l h h l x bst burst stop row active l h l h ba/ca/a10 read/reada terminate burst, new read : determine ap 13 l l l l ba/ca/a10 writ/writa terminate burst, start write : determine ap 13,14 l l h h ba/ra act illegal 9 l l h l ba/a10 pre/pall termi nate burst, pre-charging 10 l l l h x ref/self illegal read l l l l op-code mrs illegal h x x x x desl continue burst to end write recovering l h h h x nop continue burst to end write recovering l h h l x bst burst stop row active l h l h ba/ca/a10 read/reada terminate burst, start read: determine ap 7, 8 13,14 l l l l ba/ca/a10 writ/writa terminate burst, new write: determine ap 7 13 l l h h ba/ra act illegal 9 l l h l ba/a10 pre/pall termi nate burst, pre-charging 15 l l l h x ref/self illegal write l l l l op-code mrs illegal h = high level, l = low level, x = high or low level (don't care)
em48amm1684vtg jun. 2010 17/20 www.eorex.com 4. operative command table (continued) (note 7) remark h = high level, l = low level, x = high or low level (don't care), ap = auto pre-charge current state /cs /r /c /w addr. command action notes h x x x x desl continue burst to end pre-charging l h h h x nop continue burst to end pre-charging l h h l x bst illegal l h l h ba/ca/a10 read/reada illegal 9 l h l l ba/ca/a10 writ/writa illegal 9 l l h h ba/ra act illegal 9 l l h l ba, a10 pre/pall illegal 9 l l l h x ref/self illegal read with ap l l l l op-code mrs illegal h x x x x desl burst to end write recovering with auto pre-charge l h h h x nop continue burst to end write recovering with auto pre-charge l h h l x bst illegal l h l h ba/ca/a10 read/reada illegal 9 l h l l ba/ca/a10 writ/writa illegal 9 l l h h ba/ra act illegal 9 l l h l ba, a10 pre/pall illegal 9 l l l h x ref/self illegal write with ap l l l l op-code mrs illegal h x x x x desl nop enter idle after t rp l h h h x nop nop enter idle after t rp l h h l x bst illegal l h l h ba/ca/a10 read/reada illegal 9 l h l l ba/ca/a10 writ/writa illegal 9 l l h h ba/ra act illegal 9 l l h l ba, a10 pre/pall nop enter idle after t rp l l l h x ref/self illegal pre-charging l l l l op-code mrs illegal h x x x x desl nop enter idle after t rcd l h h h x nop nop enter idle after t rcd l h h l x bst illegal l h l h ba/ca/a10 read/reada illegal 9 l h l l ba/ca/a10 writ/writa illegal 9 l l h h ba/ra act illegal 9,16 l l h l ba, a10 pre/pall illegal 9 l l l h x ref/self illegal row activating l l l l op-code mrs illegal
em48amm1684vtg jun. 2010 18/20 www.eorex.com 4. operative command table (continued) (note 7) current state /cs /r /c /w addr. command action notes h x x x x desl nop enter row active after t dpl l h h h x nop nop enter row active after t dpl l h h l x bst nop enter row active after t dpl l h l h ba/ca/a10 read/reada start read, determine ap l h l l ba/ca/a10 writ/writa new write, determine ap 14 l l h h ba/ra act illegal 9 l l h l ba, a10 pre/pall illegal 9 l l l h x ref/self illegal write recovering l l l l op-code mrs illegal h x x x x desl nop enter pre-charge after t dpl l h h h x nop nop enter pre-charge after t dpl l h h l x bst nop enter pre-charge after t dpl l h l h ba/ca/a10 read/reada illegal 9,14 l h l l ba/ca/a10 writ/writa illegal 9 l l h h ba/ra act illegal 9 l l h l ba, a10 pre/pall illegal l l l h x ref/self illegal write recovering with ap l l l l op-code mrs illegal h x x x x desl nop enter idle after t rc l h h x x nop/ bst nop enter idle after t rc l h l x x read/writ illegal l l h x x act/pre/pall illegal refreshing l l l x x ref/self/mrs illegal h x x x x desl nop l h h h x nop nop l h h l x bst illegal l h l x x read/writ illegal mode register accessing l l x x x act/pre/pall/ ref/self/mrs illegal remark h = high level, l = low level, x = high or low level (don't care), ap = auto pre-charge note 7: all entries assume that cke was active (high level) during the preceding clock cycle. note 8: if all banks are idle, and cke is inactive (low level), sdram will enter power down mode. all input buffers except cke will be disabled. note 9: illegal to bank in specified states; function may be legal in the bank indicated by bank address (ba), depending on the state of that bank. note 10: if all banks are idle, and cke is inactive (low level), sdram will enter self refresh mode. all input buffers except cke will be disabled. note 11: illegal if t rcd is not satisfied. note 12: illegal if t ras is not satisfied. note 13: must satisfy burst in terrupt condition. note 14: must satisfy bus contention, bus turn around, and/or write recovery requirements. note 15: must mask preceding data which don't satisfy t dpl . note 16: illegal if t rrd is not satisfied.
em48amm1684vtg jun. 2010 19/20 www.eorex.com 5. command truth table for cke cke current state n-1 n /cs /r /c /w addr. action notes h x x x x x x invalid, clk (n ? 1) would exit self refresh l h h x x x x self refresh recovery l h l h h x x self refresh recovery l h l h l x x illegal l h l l x x x illegal self refresh l l x x x x x maintain self refresh h h h x x x x idle after t rc h h l h h x x idle after t rc h h l h l x x illegal h h l l x x x illegal h l h x x x x illegal h l l h h x x illegal h l l h l x x illegal self refresh recovery h l l l x x x illegal h x x x x x x invalid, clk(n-1) would exit power down l h x x x x x exit power down idle power down l l x x x x x maintain power down mode h h h x x x refer to operations in operative command table h h l h x x refer to operations in operative command table h h l l h x refer to operations in operative command table h h l l l h x refresh h h l l l l op-code refer to operations in operative command table h l h x x x refer to operations in operative command table h l l h x x refer to operations in operative command table h l l l h x refer to operations in operative command table h l l l l h x self refresh 17 h l l l l l op-code refer to operations in operative command table both banks idle l x x x x x x power down 17 h x x x x x x refer to operations in operative command table row active l x x x x x x power down 17 h h x x x x refer to operations in operative command table h l x x x x x begin clock suspend next cycle 18 l h x x x x x exit clock suspend next cycle any state other than listed above l l x x x x x maintain clock suspend h = high level, l = low level, x = high or low level (don't care) note 17: self refresh can be entered only from the both banks idle state. power down can be entered only from both banks idle or row active state. note 18: must be legal command as defined in operative command table
em48amm1684vtg jun. 2010 20/20 www.eorex.com package description 54-pin plastic tsop-ii (400mil)

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